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Rate guarantees and overload protection in input-queued switches

机译:输入排队开关中的速率保证和过载保护

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Despite increasing bandwidth demand and the significant research and commercial activity in large-scale terabit routers for multi-gigabit/s links, many current switch designs do not provide adequate support for rate guarantees. In particular, designs based on the popular combined-input/output-queueing (CIOQ) paradigm have unpredictable performance despite implementing sophisticated scheduling schemes on egress links, because the crossbar arbitration between ingress and egress links is done without regard to desired rate guarantees or prevailing traffic conditions. This work describes the design of an input-queued switch system and its associated arbitration and rate allocation algorithms that achieve both absolute rate guarantees and proportional bandwidth sharing even under overloaded or adversarial traffic. Our algorithms are simple and scalable and require a switch speedup of two to provide rate guarantees; we give the theoretical justification and report on simulation results that justify our claims. A semiconductor chipset based on variants of these algorithms for routers with an aggregate capacity of 160 Gbps with links up to 10 Gbps is now commercially available, and a second-generation chipset supporting 640 Gbps is also available.
机译:尽管带宽需求不断增长,并且大型千兆位路由器针对多千兆位/秒的链路进行了大量的研究和商业活动,但许多当前的交换机设计仍无法为速率保证提供足够的支持。尤其是,尽管在出口链路上实施了复杂的调度方案,但基于流行的组合输入/输出队列(CIOQ)范例的设计仍具有不可预测的性能,因为在入口和出口链路之间进行交叉开关仲裁时,并没有考虑所需的速率保证或普遍的速率交通状况。这项工作描述了输入排队交换系统的设计及其相关的仲裁和速率分配算法,即使在过载或敌对流量下,该算法也可以实现绝对速率保证和比例带宽共享。我们的算法简单且可扩展,需要将开关速度提高两个以保证速率。我们给出理论上的依据,并就可证明我们的主张正确的模拟结果进行报告。现在,基于这些算法的变体的用于路由器的半导体芯片组的总容量为160 Gbps,链路最高可达10 Gbps,现已上市,并且还提供了支持640 Gbps的第二代芯片组。

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