application specific integrated circuits; integrated circuit testing; integrated circuit design; fault diagnosis; electronic engineering computing; logic testing; delay circuits; automatic test pattern generation; low overhead delay testing; IBM ASIC; chip geometries shrink; cost effective delay test methodology; burdened IC design; transition fault coverage; ASIC business; design automation software; stuck-at fault baseline; random spot timing delay defects;
机译:使用低架空内置延迟传感器的新型延迟故障测试方法
机译:低开销的可测试性设计,用于基于扫描的延迟故障测试
机译:用于基于扫描的延迟故障测试的低开销设计可测试性
机译:asics的低开销延迟测试
机译:在典型的ASIC设计流程中处理测试问题。
机译:ASIC1和ASIC3在炎症肌肉损伤后痛觉过敏症的发展中发挥着不同的作用
机译:混合延迟扫描:用于高故障覆盖和紧凑测试集的低硬件开销扫描延迟测试技术