Non-deterministic DUT behavior during functional testing of high speed serial busses: challenges and solutions

摘要

The characteristics defining non-determinism for PCI Express busses are explored. The RapidIO/sup /spl reg// bus is used as a point of comparison. ATE architecture is proposed to significantly reduce the yield and throughput impact of random output. A specific architecture is explored and proposed for real-time pass/fail analysis of HSS data streams in the ATE environment.