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Gate oxide integrity improvement by optimising poly deposition process

机译:通过优化多晶硅沉积工艺来提高栅极氧化物的完整性

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The gate oxide integrity of oxide thickness 13.5 nm has been studied for different amorphous poly deposition conditions. The poly grain was varied by the poly deposition conditions. The study, which was carried out on BiCMOS devices, showed substantial reliability degradation in the gate oxides when using amorphous poly deposition at temperatures of 550 /spl deg/C versus 530 /spl deg/C and thickness of 60 nm versus 65 nm. A possible mechanism for the drastic reliability degradation is the protrusion of poly grains into the softening oxide at high temperature.
机译:对于不同的非晶多沉积条件,已经研究了厚度为13.5 nm的栅氧化层的完整性。多晶硅颗粒根据多晶硅沉积条件而变化。在BiCMOS器件上进行的研究表明,当在550 / spl deg / C与530 / spl deg / C的温度下以及60 nm与65 nm的厚度下使用非晶态多晶硅沉积时,栅极氧化物的可靠性大大降低。可靠性急剧下降的一种可能机制是,在高温下,晶粒会突入软化氧化物中。

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