Performance of 155Mbps clock/data recovery circuits on heavy loaded PLDs

摘要

This paper discusses the performance of internal clock and data recovery mechanisms integrated in low-cost FPGA environments. Two designs are used for this analysis, using a data sampling system with phase detection and decision logic to select the most appropriate sample either as the recovered data or as the most appropriate phase for the recovered clock. These mechanisms have been implemented in low cost PLDs from major manufactures. These PLDs have been heavily loaded with typical communications circuit functions, and the performance of the clock/data recovery circuits has been analyzed. The results show that different architectures behave differently, but internal noise can significantly impair the performance of the circuit. This poses large difficulties to the re-usage of these blocks as virtual components.