logic partitioning; VLSI; minimisation of switching nets; search problems; genetic algorithms; circuit optimisation; iterative methods; logic CAD; circuit layout CAD; integrated circuit layout; VLSI netlist partitioning; iterative heuristics; PowerFM heuristic; power consumption minimization; initial solution generator; multiobjective optimization; ISCAS-85/89 benchmark circuits; circuit partitioning; min-cut gain calculation; timing performance; cut-set cost function; switching probabilities; Tabu search; genetic algorithm;
机译:VLSI多目标网表分区的进化算法
机译:禁忌搜索:用于网表分区的元启发式方法
机译:禁忌搜索:用于网表分区的元启发式方法
机译:增强VLSI网表分区迭代启发式的表现
机译:多目标VLSI网表分区的演进技术。
机译:在线相衬成像中基于衰减分区的迭代相位检索算法的性能分析
机译:提高VLsI NETLIsT分区迭代启发式的性能