A single-cycle (32/spl times/32+32+64)-bit multiply/accumulate unit for digital signal processing and public-key cryptography

摘要

This paper presents the design and implementation of a single-cycle multiply/accumulate (MAC) unit for 32-bit RISC cores. Our design facilitates not only the processing of common DSP routines but also arithmetic with very long integers. The proposed MAC unit can perform a variety of operations including (32/spl times/32)-bit signed/unsigned multiplication, (32/spl times/32+64)-bit signed/unsigned multiplication-accumulation, and (32/spl times/32+32+32)-bit multiplication-accumulation on unsigned integers. The latter one is the core operation of multiple-precision multiplication and hence very useful for public-key cryptography. We introduce a radix-4 Booth multiplier that implements the mentioned functionality with a minimum number of full adder cells arranged in an optimized array structure. Our experimental implementations based on a 0.6 /spl mu/m standard cell library show that the MAC unit consists of roughly 8,000 gates and has a delay of less than 25 ns.