A two-step diagnosis flow, coarse-grain and fine-grain, is presented in order to identify a faulty element in the FPGA interconnects. The fault models used for interconnect are open, resistive-open, and bridging fault. The coarse-grain phase identifies the faulty net, the routing between two consecutive sequential elements in the FPGA. This phase is performed by just post-processing tester results for the test configurations used for interconnect testing. During the fine-grain step, the faulty net is rerouted without using some of the resources used in the original routing. The faulty element, programmable switch or wire segment, is uniquely identified based on the tester output for the rerouted configurations. Effective search methods are exploited in order to minimize the number of test configurations and the total diagnosis time. This method is implemented on real FPGA chips and verified using hardware fault emulation.
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