^4fChip Complexity Requires FA Tool Integration to Speed Time to Localization

摘要

^7fProcess issues mean yield loss and thus must be addressed as soon as possible to optimize profitability. Many techniques currently exist to monitor fabrication processes, but failures are still found at wafer test. Yield losses can be caused by random defects such as resistive vias and stringers or by designs vulnerable to critical dimensions. In both cases, ATE (Automated Test Equipment) readily identifies failures. However, localization is key to improving yield and ATE does not in general localize faults to the node level. Accurate localization enables the specific fabrication process step to be corrected or the specific area to be redesigned. At 130nm and below, failure analysis tools are obsolete in being able to localize faults quickly and precisely in advanced integrated circuits. Tools such as laser scanning microscopy, thermal laser stimulation, photo-emission microscopy and time resolved photon emission are needed by the failure analyst for fault localization on wafers. Integrating these tools and improving their performance dramatically reduces time to localization. Improved spatial resolution, sensitivity, and time resolution are needed as geometries shrink, operating voltages drop, and operating frequencies increase, respectively. The complexity of today's ICs results in some faults only being evident during a certain vector of a test loop, thus full stimulus wafer probing is sometimes required. This is only possible if the device under investigation is stimulated. Details of the localization of different faults are discussed along with the technology and process issues, which are creating the particular failures.