Low voltage CMOS active pixel sensor design methodology with device scaling considerations

摘要

In this paper, the design methodology and trade-offs for low voltage CMOS active pixel sensors (APS) are studied. As a result of device scaling, the power supply voltage has to be scaled at the same time. However, with the conventional APS architecture, the swing available for analog to digital conversion is significantly reduced. A new architecture with PMOS reset transistor can increase the APS swing by one V/sub T/ (threshold voltage) at the expense of extra area required for the N-well. This extra area can be compensated by using transistors with reduced dimensions. The trade-off between area and power supply voltage over 4 generations of technologies is studied and compared.