Performance Verification Scheme for Data-Driven Real-time Processing

摘要

The authors aim at realizing super-integrated data-driven processor in one-chip, for building multi-media networking environment. This paper discusses implementation for estimation schemes of turnaround time and throughput in program execution, for building interactive prototyping environment to design the processor architecture. This environment realizes symbolic execution to support detecting side-effects as well as incorrectness that users' requirements are not correctly reflected to specification. Furthermore, as requirements on performance and time constraints must be satisfied in multi-media networking, the environment also supports verification facility on performance and time constraints. This paper discusses minimizing computation costs in es-timaling turnaround time and, throughput, and then this paper proposes that the system preserves partial results of estimation by utilizing hierarchy of specification and the system reuses them as long as possible. Through the preliminary evaluations, it has been shown that interactive verification on turnaround time and throughput can be realized regardless of program size.