A CMOS linage Sensor with Parallel Analog Processing Unit for Transformations and Spatial Convolutions

摘要

We present a prototype implementation of an image sensor chip with on-chip block transformation or spatial convolution capabilities and digital output. The digital kernel-coefficients for transformations or convolutions can be set arbitrarily. The chip comprises a 128 x 64 pixel CMOS image sensor, signal conditioning, a low-power mixed-signal multiplier array and a dedicated multi-input pipelined A/D converter. The design is scalable up to CIF size (352 x 288 pixels) with a frame rate of 30 frames per second.