This paper describes the deisgn and implementation of soft-decision Viterbi decoder on TMS320C6201 DSP developed by Texas Instruments (TI) in 1998. With the incomparable operating speed, which is 200MHz (5-ns cycle time), the TMS320C6201 DSP can achieve the performance of up to 1600 million instructions per second (MIPS) and consequently has gained more and more popularity in many applications. IN this paper a soft-decision Viterbi decoder is implemented on the TMS320C6201 Evaluation Module (EVM) board with the code rate 1/3 and constraint length 9. Our originally aim was to achieve a decoding rate of 32Kbits/s which is requested by the WCDMA recommendation. To our delighted, however, we have finally implemented a Viterbi decoder with the decoding rate of 88Kbits, which is quite comparable to what has been developed on FPGAs. We also mention some bottleneck problems of TMS320C6201 DSP and some applications of this kind of Viterbi decoder at the end of this paper.
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