CASPER: Concurrent hardware-software co-synthesis of hard real-timeaperiodic and periodic specifications of embedded system architectures

摘要

Hardware-software co-synthesis of an embedded system requiresmapping of its specifications into hardware and software modules suchthat its real-time and other constraints are met. Embedded systemspecifications are generally represented by acyclic task graphs. Manyembedded system applications are characterized by aperiodic as well asperiodic task graphs. Aperiodic task graphs can arrive for execution atany time and their resource requirements vary depending on how theirconstituent tasks and edges are allocated. Traditional approaches basedon a fixed architecture coupled with slack stealing and/or on-linedetermination of how to serve aperiodic task graphs are not suitable forembedded systems with hard real-time constraints, since they cannotguarantee that such constraints would always be met. In this paper, weaddress the problem of concurrent co-synthesis of aperiodic and periodicspecifications of embedded systems. We estimate the resourcerequirements of aperiodic task graphs and allocate execution slots onprocessing elements and communication links for executing them. Ourapproach guarantees that the deadlines of both aperiodic and periodictask graphs are always met. We have observed that simultaneousconsideration of aperiodic task graphs while performing co-synthesis ofperiodic task graphs is vital for achieving superior results compared tothe traditional slack stealing and dynamic scheduling approaches. To thebest of our knowledge, this is the first co-synthesis algorithm whichprovides simultaneous support of periodic and aperiodic task graphs withhard real-time constraints. Application of the proposed algorithm toseveral examples from real-life telecom transport systems shows that upto 28% and 34% system cost savings are possible over co-synthesisalgorithms which employ slack stealing and rate-monotonic scheduling,respectively