Large PMOS FETs with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron integrated circuits. These clamps divide the supply voltage maong several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during the ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The designs for high voltage are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power s upply lines.
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机译：可以安排具有多个栅极的大型PMOS FET，为亚微米集成电路中的高压片上电源提供ESD保护。这些钳位电路将电源电压分配给多个栅极氧化物。大串联FET随附的电路可在ESD期间为高脉冲电流提供接近最大的栅极驱动。由于可以使用最小尺寸，并且因为在堆叠的栅极之间不需要接触，所以布局被密集地包装。高压设计是大型PMOS FET ESD钳位和定时驱动电路的扩展，这些钳位用于钳位普通的片上电源线。
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