Improving simulation accuracy in design methodologies for dynamically reconfigurable logic systems

摘要

This paper presents a new approach to the simulation of Dynamically Reconfigurable Logic (DRL) systems, which offers better accuracy of modelling dynamic reconfiguration than previously reported simulation techniques. Our method, named Clock Morphing, is based on modelling dynamic reconfiguration via a reconfigured module clock signal while using a dedicated signal value to indicate dynamic reconfiguration. We also discuss problems associated with the other DRL simulation techniques, describe the main principles of the proposed simulation method and evaluate its feasibility by implementing of a Clock Morphing based DRL simulation in VHDL.