A s integrated circuit sizes decrease below 0.25 microns, device performance will no longer improve at the same rate as for past generations because of RC interconnect delay which becomes significant as compared to the intrinsic gate delay. Parallel approaches to address this are to use a lowe resistance metal (i.e., copper instead of aluminum) and to use a dielectric material with a dielectric constant significantly below that of dense silica (approx 4). Recently, considerable progress has been made in development of thin films of nanoporous silica for these applications. Advantages include high thermal stability, samll pore size, similarity to conventional spin-on depositionprocesses and spin-on glass precursors and final material (silica). The dielectric constant of nanoporous silica can be tailored between approx 1 an 3 which allows its' implementation at multiple technology nodes in integrated circuit manufacture.
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