Local oxidation of silicon (LOCOS) isolation processes are severely challenged by deep sub-micron CMOS design rules in two aspects; controlling active area encroachment and lifting at minimum active area line widths and corners; and preventing field oxide thinning at minimum active area spacing. This paper describes the use of dark-field weak-beam transmission electron microscopy to obtain a three-dimensional quantitative measurement of the topography of the Si/SiO_2 interface. We find that standard LOCOS can be optimised for isolation down to 0.3 micron geometries.
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