A 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at 1.3GHz with 37.4W power dissipation in the laboratory. The chip contains over 190M transistors with 19M in logic circuits. The chip size is 18.14mm x 15.99mm. The error detection and recovery mechanism is implemented for execution units and data path logic circuits in addition to on-chip arrays to detect and recover from data logic error. This processor is developed by using mostly in-house CAD tools.
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机译：第5代SPARC64处理器采用130纳米SOI CMOS工艺制造，具有8层铜金属镀层。在实验室中，它的运行频率为1.3GHz，功耗为37.4W。该芯片包含超过190M的晶体管和19M的逻辑电路。芯片尺寸为18.14mm x 15.99mm。除了片上阵列以外，还为执行单元和数据路径逻辑电路实现了错误检测和恢复机制，以检测并从数据逻辑错误中恢复。该处理器是通过使用大多数内部CAD工具开发的。
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