A programmable clock generator with 50 to 350 MHz lock range forvideo signal processors

摘要

Using 0.5-μm CMOS triple-layer Al technology, a programmableclock generator based on a PLL (phase-locked loop) circuit has beendeveloped for use as an on-chip clock generator in a 300-MHz videosignal processor. It generates an internal clock whose frequency is anintegral multiple of an external clock frequency, and its oscillatingfrequency ranges from 50 to 350 MHz. Experimental results show that theclock generator generates a 297-MHz clock with jitter reduced to 180 pswith a 27-MHz input clock, and that it oscillates at up to 348 MHz witha 31.7-MHz input clock