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Receiver design issues for parallel optical interconnections fabricated in the FET-SEED technology

机译:FET-SEED技术中制造的并行光学互连的接收器设计问题

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Abstract: This paper discusses the sensitivity limitations of smart pixel optical receiver arrays fabricated in the GaAs FET-SEED technology. Four circuit topologies (high impedance clamped, resistive load partially clamped, differential transamp, and common gate) are compared. Simulated and experimental data are presented. !29
机译:摘要:本文讨论了采用GaAs FET-SEED技术制造的智能像素光接收器阵列的灵敏度局限性。比较了四种电路拓扑(高阻抗钳位,部分钳位的电阻负载,差分放大器和公共栅极)。给出了仿真和实验数据。 !29

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