Presents a genetic approach to the placement problem of analog LSI chip designs. The emphasis is the application of our approach to a real-world problem. The objective of this problem is to minimize the overall net length and the layout area under many electrical constraints among elements, and under the condition of making the subsequent routing task easy. Our approach is based on a polycell placement style to make the routing easy and it minimizes several cost functions. Computational experiments show the efficiency of our genetic algorithm (GA) compared to the tabu search (TS). The concatenation of GA and TS, and a dynamic adjustment of the mutation rate are introduced, and their effectiveness is shown.
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