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Design and performance evaluation of a parallel architecture for the Boltzmann machine

机译:Boltzmann机器的并行体系结构的设计和性能评估

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The Boltzmann Machine (BM) is a statistical neural model well suited to the approximate solution of combinatorial optimization problems and massively parallel implementations. In this paper we present a dedicated parallel architecture for the BM, organized as an array of processing elements (PEs) that communicate with a host workstation through a linear shared bus. Each PE contains a low-cost general purpose processor (MC68000), local memory, synchronization and initialization hardware. The host executes the sequential part of the BM procedure and drives the processor array through a fork-join mechanism to start the parallel routines. The paper shows a set of measurements on a first prototype and demonstrates interesting speedup/cost figures with respect to state-of-the-art workstations when attacking large optimization problems with a proper number of PEs.
机译:玻尔兹曼机(BM)是一种统计神经模型,非常适合组合优化问题和大规模并行实现的近似解决方案。在本文中,我们提出了一种专用于BM的并行架构,其组织为一系列处理元件(PE),它们通过线性共享总线与主机工作站进行通信。每个PE都包含一个低成本的通用处理器(MC68000),本地存储器,同步和初始化硬件。主机执行BM过程的顺序部分,并通过fork-join机制驱动处理器阵列以启动并行例程。本文展示了在第一个原型上进行的一组测量,并展示了当使用适当数量的PE攻击大型优化问题时,相对于最新型工作站而言有趣的加速/成本数据。

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