一种可扩展的并行处理器模型设计及性能评估

摘要

开发和设计并行处理器是一种有效提高图像处理速度的方法。本文分析了国内外近年来各种并行处理器的发展状况，提出了一种可扩展的面向图像处理的并行处理器架构（EPIP）和专用指令集。该架构复用多个流处理单元（SP）以单指令多数据流方式组织充分实现了数据级并行。单个流处理单元内采用超长指令字（VLTW）技术和并行多线程技术（SMT）分别实现指令级并行和任务级并行。专用指令集支持对私有寄存器和共享寄存器的混合寻址。利用SystemVerilog对该架构进行时钟精确建模，并将常见图像处理算法在该结构上进行了映射。最后给出了EPIP初步的性能评估结果。%Adopting the parallel processor to process image in parallel is an effective way to improve the processing rate. In this paper, an extensible parallel processor for image processing （EPIP） and spe- cific instruction sets are proposed, based on the analysis of recent international and national progress of parallel processors. Many stream processor units （SP） are reused in the developed processor, which are organized in the single instruction multiple data （SIMD） way to fully exploit the data-level parallel. The very long instruction word （VLIW） and simultaneous muhithreading （SMT） technologies are implemented in a single SP, which realizes the instruction-level parallel （ILP） and task-level parallel （TLP） respec- tively. Specific instruction sets support the hybrid addressing of private registers and shared registers. The SystemVerilog is employed to build up the cycle-based simulation model of the proposed architecture, and several common image processing algorithms are mapped to the simulator. Finally, the preliminary per- fonnance of EPIP is given.