Design for testability using behavioral models

摘要

The authors present a systematic approach to analog design-for-testability which uses behavioral models for fault simulation so that objective comparisons can be made between alternative test configurations. This technique of design-for-testability is shown to be especially well suited to an ASIC's (application-specific integrated circuits') environment because the models can be reused and combined to form a library. The fault models should improve with time as more data are collected for a given block. For this reason, a design/experimentation environment has been developed to provide feedback to the system designers. The normal models can also be used to decide what specifications a block will need to function properly in a given system. This is very useful in the design phase for determining how well blocks will fit together, or how much linearity or signal swing a given block will need to achieve a certain high-level system specification.