Fixed-node routing architecture and its performance in ATM networks

摘要

The architecture and performance of fixed-node virtual channel (VC) routing in asynchronous transfer mode (ATM) networks is studied. In fixed-node routing, only the nodes are specified, and any of the available parallel links between nodes may be used. Applying the fixed-node routing architecture in ATM networks has the advantages of more efficient use of network resources, better availability/reliability and performance, and the ability to support superrate services. The sequencing problem associated with this approach in conventional packet-switched networks can be easily solved in the ATM environment. An analysis is presented of the performance of this routing architecture for an internally nonblocking ATM switch with partially shared output buffers based on a discrete-time D/sup (A)//D/c/B queuing system for general input traffic. A D/sub 1/+ . . . +D/sub N//D/c/B queuing system is used for deterministic traffic. It is shown that the fixed-node routing architecture yields better performance in terms of delay, loss probability, channel utilization, and switch throughput than its fixed-path counterpart.