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Fault simulation in a pipelined multiprocessor system

机译:流水线多处理器系统中的故障仿真

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The authors describe fault simulation algorithms for the MARS hardware accelerator. Two algorithms are considered. The first, serial fault simulation, has a performance that is linear in the number of faults. Its performance is easily predictable and it takes full advantage of the true-value simulation speed of the accelerator; it is also easy to implement. The second algorithm, concurrent fault simulation, is found to have a performance that is nonlinear in the number of faults. It also requires either a large amount of memory or a dynamic memory management, both of which are difficult to implement in an accelerator. Yet the concurrent method has the advantage of more efficient event processing and less duplicated effort. Combining the features of both algorithms, a fixed-memory, multipass, concurrent algorithm is developed for MARS.
机译:作者介绍了MARS硬件加速器的故障仿真算法。考虑两种算法。第一个是串行故障仿真,其性能在故障数量上是线性的。它的性能很容易预测,并且充分利用了加速器的真实值仿真速度;它也很容易实现。发现第二种算法,并发故障仿真,具有在故障数量上非线性的性能。它还需要大量内存或动态内存管理,这两者都难以在加速器中实现。然而,并发方法的优点是事件处理效率更高,重复工作更少。结合这两种算法的特点,为MARS开发了固定内存,多通道并发算法。

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