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Efficient ASIC Implementation of a NB-IoT Security Co-processor

机译:NB-IoT安全协处理器的高效ASIC实现

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This work implements a hardware acceleration of selected confidentiality and integrity algorithms for Long Term Evolution (LTE) based on SNOW3G and ZUC stream ciphers. Structural similarities between both ciphers were utilized to combine a single configurable accelerator. Implementation is primarily optimized to cater for NB-IoT devices where lower resources considerations exist. Different implementation approaches are compared targeting a 130 nm technology resulting in an optimized hardware accelerator for 100 Mbps rate and utilizing cell area of 35.7 kGE. Maximum GDSII energy consumption after PnR is 1.74 pJ/bit. For the sake of comparison with current LTE cipher cores, the co-processor was characterized using a 65 nm technology at 2 Gbps rate achieving 47% area reduction for the cipher core without sacrificing average power consumption.
机译:这项工作基于SNOW3G和ZUC流密码,为长期演进(LTE)实现了所选机密性和完整性算法的硬件加速。两个密码之间的结构相似性被用于组合单个可配置的加速器。实施主要是针对满足较低资源考虑因素的NB-IoT设备进行优化的。比较了针对130 nm技术的不同实现方法,从而获得了针对100 Mbps速率的优化硬件加速器并利用了35.7 kGE的单元面积。 PnR之后的最大GDSII能耗为1.74 pJ / bit。为了与目前的LTE密码核心进行比较,协处理器的特征是使用65 nm技术以2 Gbps的速率实现了密码核心面积减少47%,而又不牺牲平均功耗。

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