A Fully Integrated On-Chip Inductive Digital Isolator: Design Investigation and Simulation

摘要

This work presents the implementation and simulation of a fully integrated on-chip inductive digital isolation system in AMS 0.35 µm CMOS process. The aim of this work is to investigate the transformer design of the isolation barrier in a digital isolator system. Firstly, both capacitive and inductive coupling techniques are presented and compared in terms of effective area, power consumption and propagation delay. Then, a transformer-based inductive digital isolator system chip prototype is presented using two different customized transformer designs. The on-chip transformer’s secondary coil is implemented in first metal layer (M1), whereas the primary coil is constructed on metal 2 (M2) and metal (M3) in order to examine the system functionality and isolation capability. The system occupies 2 mm² of silicon area and achieves approximately a 15 ns propagation delay for a 15 MHz input pulse-width modulated (PWM) signal.