Efficient Functional Locking of Behavioral IPs

摘要

The protection of the Intellectual Property (IP) has emerged as one of the most serious areas of concerns in the semiconductor industry. Logic locking has shown to lead to good results, with little overhead against Integrated Circuit (IC) over-production and IP piracy by untrusted end-users or foundry. Unfortunately new attack techniques appear each time a new locking mechanisms is presented to exploit its weakness. Some include path sensitization and more recently SAT-based attacks. This work proposes a functional locking mechanisms for behavioral IPs (BIPs) that exploits the internal structure of behavioral descriptions when synthesized with High-Level Synthesis (HLS). In particular the generation of a Finite State Machine (FSM) and a datapath. Our proposed locking mechanism increases the key size by breaking it into multiple pieces, each applied at a unique FSM state. Applying the incorrect key at any of the states leads to an invalid results. Breaking our proposed locking mechanism is much harder than previous work as the attacker would need to try all possible permutations of keys to find the correct key, thus making this virtually unbreakable. Moreover, we insert the key at the BIP itself, which implies that the locking logic is shared with the BIP logic, hence making it more robust against removal attacks. Experimental results show that the proposed locking mechanism works very well with minimal area and delay overheads for different key sizes.