On the Reliable Performance of Sequential Adders for Soft Computing

摘要

Addition is a significant operation in soft computing, several sequential adder designs have been proposed in the technical literature. These adders show different operational profiles, some of them are inspired by biological networks or the probabilistic nature of nanometric devices (such as the Lower-part OR Adder (LOA) and the Probabilistic Full Adder (PFA)). This paper deals with the reliability assessment and comparison of these sequential adder implementations. A new metric referred to as the mean error distance (MED) is proposed as a unified figure for evaluating the reliability of both probabilistic and deterministic adders. Reliability is analyzed using the so-called sequential probability transition matrices (S-PTMs) with respect also to error masking (as occurring due to the sequential nature of the addition process). A baseline sequential adder implementation, referred to as the Lower-bit Ignored Adder (LIA), is used as a benchmark for evaluating the other implementations. It is shown that compared with the LIA, the PFA has a better reliability at a small gate error rate, but at the cost of a larger overhead in area and therefore static power consumption. The LOA achieves a good tradeoff between reliability, area, power and delay compared to the LIA and PFA implementations.