Debug Aware AXI-based Network Interface

摘要

With a significant increase in the complexity of cores and their intercommunications, there is a need to review and enhance traditional debug methods for System on Chips (SoCs). As new SoCs tend to have many cores, the interactions among cores through functional interconnects such as bus or Network on Chips (NoCs) are becoming so complex. Therefore, debug techniques should address not only validation of the computational part of a design but such techniques have to monitor and validate the communication and synchronization among cores inside SoCs. In this paper, we consider NoC as a functional interconnection among cores and propose debug aware network interface (NI) which is compatible with AXI standard. The proposed interface enables provides a mechanism for cross-trigger debugging. Transactions issued by a processing element connected to the proposed debug aware NI are monitored by the proposed cross-trigger unit and trace data and trigger events will be extracted and routed to another processing element or Shared Debugging Unit (SDU). SDU combines debug traces from different processing elements. The major benefits of using our proposed architectures for debugging over traditional techniques are as follows: 1) the proposed debug aware NI can detect, mark and bypass severe faulty conditions such as deadlocks resulting from design errors or electrical faults in real time 2) there is no need for a large internal trace memory inside processing element because SDU can communicate to the external memory 3) debugging of applications which are running on multiple processors can facilitate by means of available features inside the proposed trigger mechanism.