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Advanced Inspection Methodology for the Maximum Extension of Nitride Test Wafer Recycling

机译:最大限度地扩展氮化物测试晶圆回收的高级检查方法

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Defect control is an important part of semiconductor manufacturing as it ensures device quality. In general, defect control is accomplished using numerous types of inspection equipment to find excursion wafers or process tools and help identify the defect source during production. However, the balance between productivity and inspection needs to be calculated carefully to minimize the manufacturing cost. In general, achieving high productivity is the priority for a semiconductor factory, requiring inspection cost saving while still maintaining stable device yield. As one of the many inspection points, all incoming test wafers are qualified by unpatterned wafer defect inspectors, which raises cost concerns for manufacturing. Extending test wafer reuse lifetime is a common target for cost savings. In this paper, an advanced inspection methodology is described to achieve the maximum recycling extension of nitride (Si3 N4) deposited wafers. The inspection bottleneck of the recycling extension is not only related to increased surface roughness after film removal, but also to the inspected sensitivity shift value between pre-and post-scans. The Surfscan® SP3 and Surfscan® SP5 unpatterned wafer defect inspection systems are used for the study of recycling extension of test wafers. Furthermore, the technique of defect source analysis (DSA) is utilized to identify the suitable pre-scan sensitivity for the zero false adder goal. In summary, the optimization of the inspector’s aperture configuration for post-scan inspection can minimize the sensitivity shift value. Based on the evaluated Si3 N4 layers, 26nm pre-scan sensitivity is required to avoid false adders. Furthermore, the Surfscan SP5 is the preferred platform over the Surfscan SP3 due to the better suppression of haze and a 3x faster throughput. Up to $5 sim 7$ wafer recycle times for test wafers can be achieved for the demonstrated Si3 N4 layers, which can save 84% incoming wafer purchasing.
机译:缺陷控制是半导体制造的重要组成部分,因为它可以确保器件质量。通常,使用多种类型的检查设备来查找缺陷晶圆或工艺工具,并在生产过程中帮助识别缺陷源,从而完成缺陷控制。但是,需要仔细计算生产率和检查之间的平衡,以最大程度地降低制造成本。通常,实现高生产率是半导体工厂的首要任务,需要节省检查成本,同时仍保持稳定的器件良率。作为众多检查点之一,所有传入的测试晶片均由无图案的晶片缺陷检查员进行鉴定,这增加了制造方面的成本问题。延长测试晶圆的再利用寿命是节省成本的共同目标。本文介绍了一种先进的检测方法,可实现氮化物(Si 3 ñ 4 )沉积的晶圆。回收利用扩展的检查瓶颈不仅与去除薄膜后表面粗糙度增加有关,而且还与扫描前后之间所检查的灵敏度变化值有关。冲浪扫描 ® SP3和Surfscan ® SP5无图案晶片缺陷检查系统用于研究测试晶片的回收扩展。此外,缺陷源分析(DSA)技术可用于为零假加法器目标识别合适的预扫描灵敏度。总而言之,优化用于扫描后检查的检查器的光圈配置可以最大程度地降低灵敏度偏移值。基于评估的硅 3 ñ 4 层,需要26nm的预扫描灵敏度,以避免加法器错误。此外,Surfscan SP5是优于Surfscan SP3的首选平台,因为它具有更好的雾度抑制能力和3倍的吞吐速度。对于演示的硅,可以达到$ 5 \ sim 7 $的测试晶圆晶圆回收时间 3 ñ 4 层,可以节省84%的晶圆采购。

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