A 100-MS/s 9-bit Charge-Injection Cell based SAR-ADC in 65nm LP CMOS

摘要

This paper presents a 9 bit resolution charge-injection cell based area-efficient SAR-ADC (ciSAR) with a maximum differential input swing of 1.4V and 10 bit linearity up to the second Nyquist zone. This is enabled by a charge pump technique as well as a charge balancing switching scheme during binary search. During the top-plate sampling operation, the non-linear comparator input capacitance is isolated from the track and hold function for linearity improvements. Furthermore the reference-free ciSAR comprises an intrinsic 4.5 dB gain tuning range with only minor SFDR and SNDR variations of less than 2 dB. The ADC is designed in a 65nm LP CMOS process and reveals 7.5 bit ENOB as well as 62 dBc SFDR up to the second Nyquist zone. Consuming only 0.02mm2 area with an aspect ratio of 1:4, the ciSAR with a 451MHz effective resolution bandwidth is suitable for highly-dense parallel sensor readout systems.