Hold Error Minimization Method on S/H Circuit Using Feedforward Neural Network as a Function Approximation

摘要

One of the most important building blocks in analog to digital converter (ADC) is sample and hold (S/H) circuit. The function of this circuit is to hold the input voltage until ADC completes the conversion process. The accuracy of S/H circuit is limited by channel charge injection and clock feedthrough. In this paper, a new method to minimize hold error in CMOS TG switch S/H circuit using feedforward neural network as function approximation is proposed. The basic idea of the proposed method is to minimize hold error by adjusting the width of NMOS transistor (W_n) and PMOS transistor (W_p) in CMOS switch numerically using a trained neural network. The performance of the proposed method is evaluated using HSPICE with 180 nm CMOS standard process. As a result, HSPICE simulation verified that hold error produced by S/H circuit whose W_p and W_n are generated using the minimization method is mostly zero. The maximum and average hold error is 20 μV and 2 μV, respectively.