Design of differential voltage mode transmitter for on-chip serial link based on method of logical effort

摘要

In the literature, voltage mode and current mode multiplexers are used for differential on-chip global interconnect transmitters. Conventionally, the Pseudo-NMOS multiplexer used in voltage mode transmitters consumes more power and has less bandwidth, whereas the current mode multiplexers operate at higher speeds at the cost of increase in power consumption. In this paper, a novel domino logic based multiplexer is proposed for differential voltage mode serial interconnect transmitter to minimize the power consumption and the speed comparable to that of current mode multiplexers. The proposed transmitter is designed using the method of logical effort and is implemented in UMC 180nm technology. The post layout simulations are carried out through Cadence Virtuso tool. From the post layout simulations, it is observed that the power consumed and the area of the proposed domino logic based multiplexer is 1.42 times and 3.77 times lower respectively and the speed comparable to that of CMOS multiplexer circuit.