Design of Floating-Point Arithmetic Unit for FPGA with Simulink?

摘要

Much of the numerical computation algorithms are dependent on the capability to perform arithmetic operations with real numbers. In digital electronics, the most common approximation of the Reals is the floating-precision format. The novelty of the paper is that the design is entirely developed as two Simulink? block diagrams for summation, subtraction and multiplication of single precision floating-point numbers, according to the IEEE 754 Standard. From these models a VHDL code is generated with the help of Simulink HDL Coder. Dataflow models are validated by simulation in Simulink?. For the experimental validation of the designed floating-point arithmetic units they are embedded in a FPGA evaluation platform. The arithmetic operations are executed with a minimum delay or within a single cycle of the respective clock. Required chip area is smaller in comparison to other open source solutions.