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Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector

机译：FPGA中位宽缩减浮点算术单元的性能分析：基于神经网络的面部检测器的案例研究

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年度 2009
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入库时间 2022-08-20 20:28:01

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1. Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector [J] . Y. Lee, Y. Choi, M. Lee, EURASIP journal on embedded systems . 2009,第3期

机译：FPGA中位宽缩减浮点算术单元的性能分析：基于神经网络的面部检测器的案例研究
2. Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector [J] . Yongsoon Lee, Younhee Choi, Seok-Bum Ko, EURASIP journal on embedded systems . 2009,第1期

机译：FPGA中位宽缩减浮点算术单元的性能分析：基于神经网络的面部检测器的案例研究
3. The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units [J] . Chi WaiYu, JulienLamoureux, Steven J. E.Wilton, International journal of reconfigurable computing . 2008,第4期

机译：具有嵌入式浮点算术单元的FPGA中的粗粒度/精细粒度逻辑接口
4. THE COARSE-GRAINED/FINE-GRAINED LOGIC INTERFACE IN FPGAS WITH EMBEDDED FLOATING-POINT ARITHMETIC UNITS [C] . Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Southern Conference on Programmable Logic . 2008

机译：具有嵌入式浮点算术单元FPGA的粗粒/细粒度逻辑界面
5. Caffeinated FPGAs: FPGA Framework for Training and Inference of Convolutional Neural Networks With Reduced Precision Floating-Point Arithmetic [D] . DiCecco, Roberto. 2018

机译：含咖啡因的FPGA：用于训练和推理卷积神经网络的FPGA框架，具有降低的精度浮点算法
6. A Model-Based Design Floating-Point Accumulator. Case of Study: FPGA Implementation of a Support Vector Machine Kernel Function [O] . Marco Bassoli, Valentina Bianchi, Ilaria De Munari 2020

机译：基于模型的设计浮点累加器。研究案例：支持向量机内核功能的FPGA实现
7. Analysis of high-performance floating-point arithmetic on FPGAs [O] . Gokul Govindu, Ling Zhuo, Seonil Choi, 2004

机译：FpGa上的高性能浮点运算分析
8. Area, and Power Performance Analysis of a Floating-Point Based Application on FPGAs [R] . Govindu, G. , Zhuo, L. , Choi, S. , 2003

机译：FpGa上基于浮点的应用的面积和功耗性能分析

Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector

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