A 44fs RMS Jitter 6GHz Limiting Amplifier in 22nm CMOS FDSOI

摘要

This paper presents a low-power, low-noise limiting amplifier for ultra low-noise wide-band clock regeneration. The proposed limiting amplifier was fabricated in 22 nm CMOS FD-SOI and reveals an outstanding measured 44 fs RMS clock jitter performance at 6GHz signal frequency consuming only 9.6 mW power at 0.9 V supply voltage and an area of 0.0021 mm². Given a 48 dB open loop gain as well as a unity gain bandwidth of 35 GHz of the limiting amplifier, a small differential sine-wave with signal level of -9.5 dBm (300 mVppd) is sufficient to generate clock signals with <; 50 fs RMS clock jitter. Given the superior noise performance of the proposed amplifier in conjunction with 22 nm CMOS FDSOI, the ultra-low noise clock generation as well as the data converter can be integrated in a single-chip solution incorporating compact, low-cost > 1 GS/s high-resolution data converter systems with a jitter induced signal-to-noise ratio of > 60 dB (10 bit ENOB). Thus, 22 nm CMOS FDSOI is a promising vehicle for high bandwidth, high-resolution data converters with on-chip clock generation.