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Python-based FPGA implementation of AES using Migen for Internet of Things Security

机译:使用Migen的AES基于Python的FPGA实现物联网安全

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Internet of things (IoT) technology is making it possible for a wide variety of end-user devices to be connected to the internet, leading to richness and accuracy of real data that would previously have needed much more cumbersome and expensive methods. But this connectedness also leads to more challenges in data security and the increased risk of cyber-attacks. Improved, and faster, security schemes have become a key requirement of these loT technologies. Field Programmable Gate Arrays (FPGAs) have been used to accelerate various cyber-security algorithms. However, while FPGAs are capable of massive computational power, through their highly parallel nature, they are generally difficult to program; and considering the design of modern encryption schemes this is posing a significant bottleneck to progress in security for these architectures. This paper investigates the use of a Python-based high-level FPGA design tool-flow for rapid prototyping of loT cryptosystems. In this paper we implement a version of the Advanced Encryption Standard (AES) algorithm, with block and key sizes of 128bits, using the Python-based tool-flow. The design is functionally verified, a Verilog hardware implementation is generated, simulated and then executed on an FPGA platform. The performance of the resulting FPGA design is analyzed in terms of resource utilization and throughput, and is compared against similar hand-written AES implementations reported in the literature. We found our FPGA implementation had a frequency of 512.742 MHz and a throughput of 65.63Gbps which is more than fast enough for most IoT applications.
机译:物联网(IoT)技术使各种各样的最终用户设备可以连接到互联网,从而导致真实数据的丰富性和准确性,而以前这些数据需要更加繁琐和昂贵的方法。但是,这种连通性还导致数据安全方面的更多挑战,并增加了网络攻击的风险。改进,更快的安全方案已成为这些loT技术的关键要求。现场可编程门阵列(FPGA)已用于加速各种网络安全算法。然而,尽管FPGA具有高度并行性,但具有强大的计算能力,但通常很难编程。考虑到现代加密方案的设计,这对这些体系结构的安全性提出了巨大的瓶颈。本文研究了基于Python的高级FPGA设计工具流程对loT密码系统快速原型化的使用。在本文中,我们使用基于Python的工具流实现了一种高级加密标准(AES)算法,其块和密钥大小为128位。对设计进行功能验证,生成,仿真并在FPGA平台上执行Verilog硬件实现。根据资源利用率和吞吐量分析了所得FPGA设计的性能,并将其与文献中报道的类似的手写AES实现进行了比较。我们发现我们的FPGA实施频率为512.742 MHz,吞吐量为65.63Gbps,对于大多数物联网应用而言,速度已经足够快。

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