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Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs

机译：针对FpGa中实际设置时间违规攻击的不同aEs实现的安全性评估

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Shivam Bhasin; Nidhal Selmane; Sylvain Guilley; Jean-luc Danger;
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年度 2014
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1. Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks [J] . Selmane N., Bhasin S., Guilley S., Information Security, IET . 2011,第4期

机译：针对专用集成电路和现场可编程门阵列针对建立时间违规攻击的安全性评估
2. Countermeasures Against DPA Attacks on FPGA Implementation of AES [J] . G. Dinesh Babu, N. Nalla Anandakumar, D. Muralidharan Journal of Artificial Intelligence . 2012,第4期

机译：DPA攻击AES的FPGA实现的对策
3. Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA [J] . G. Canivet, P. Maistri, R. Leveugle, Journal of Cryptology . 2011,第2期

机译：故障和激光故障攻击对基于SRAM的FPGA上的安全AES实现
4. Security evaluation of different AES implementations against practical setup time violation attacks in FPGAs [C] . IEEE International Worksohp on Hardware-Oriented Security and Trust . 2009

机译：不同AES实现对FPGA的实际设置时间违规攻击的不同AES实现的安全评估
5. A Low Power FPGA Implementation of the 128-bit AES Algorithm [D] . Thakkar, Himanshu Jayantilal 2018

机译：128位AES算法的低功率FPGA实现
6. Real-Time Digital Signal Processing Based on FPGAs for Electronic Skin Implementation [O] . Ali Ibrahim, Paolo Gastaldo, Hussein Chible, 2017

机译：基于FPGA的电子皮肤实现实时数字信号处理
7. Performance and Security Evaluation of AES S-Box-based Glitch PUFs on FPGAs [O] . Yamamoto Dai, Hospodar Gabriel, Maes Roel, 2012

机译：FPGA上基于AES S-Box的毛刺PUF的性能和安全性评估

Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs

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