Memory Optimization for Accelerating Hough Transform on FPGA using High Level Synthesis

摘要

In this work, we present memory optimization in Hough transform on hardware of programmable logic (PL) part of FPGAs by using array partitioning block, cyclic and complete types at different dimension and different factor on the Xilinx Vivado High Level Synthesis tool. Loop analysis was presented to extract nested loops and suitably manage the array. The experimental results show that adding array partitioning complete type at dimension 2 can be the best type to improve speed of operating time and reduce the number of resources on Zybo ZC7010-1.