A Digital PLL Based 2^nd-Order Δ∑ Bandpass Time-Interleaved ADC

摘要

This paper presents a time-interleaved (TI) VCObased band-pass ADC with a second-order bandstop noise transfer function. The proposed ADC uses a digital phase-locked loop (PLL) based architecture and employs current starved ring-oscillator as integrator which provides inherent multi-bit quantization. Thus, the proposed band-pass ADC does not need op-amps for integration and consumes low power and area. The proposed ADC is designed in 65nm CMOS and Matlab and Spectre simulations were performed to characterize the ADC. The proposed ADC achieves 61dB SNDR while consuming 0.44mW and has a Walden FoM of 63fJ/conv. step.