Approximation-Conscious IC Testing

摘要

Approximate computing Is a nascent energy-efficient computing paradigm for error-tolerant applications. However, the approximate nature of these circuits makes their testing phase quite challenging. Similarly, partial testing of ICs based on a reduced fault list is adapted to exclude some test patterns for manufacturing defects tolerated by design approximation. To streamline these processes and thus reduce yield loss and test cost, and based on distinct subsets of test patterns and fault coverage, we propose an approximation-conscious multi-level IC test flow, which classifies the output of the test process to be either: (1) a "good" defect-free 1C, (2) 7 different levels of "good-enough" partially-passed approximate ICs, or (3) a "bad" rejected IC.