A Highly Linear Ring Oscillator for VCO-based ADCs in 65-nm CMOS

摘要

We present a novel ring oscillator circuit that improves the linearity of actual circuits by mixing two kinds of delay cells. One group of delay cells is connected to a reference supply voltage while other group of cells is connected to a modulated current bias. By interleaving both groups of cells in a single ring oscillator, we obtain a highly linear variation of the oscillation frequency with respect to the analog input signal. Additionally, the delay cells are still implemented in a mostly digital way, which makes them very suitable for deep-submicron processes. The proposed structure is of special interest for the implementation of voltage-controlled oscillator based analog-to-digital converters (VCO-based ADCs), specially with open-loop configurations where the VCO nonlinear transfer function might strongly degrade the performance. Also, the fixed level cells help to sample the oscillation without residual amplitude modulation. The new structure was designed in a 65-nm CMOS process and validated through simulations in a simple VCO-based ADC architecture. The resulting third harmonic distortion (HD3) for a 600 mV_pp-amplitude differential sinusoidal input signal was equal to -79 dB, which is well-suited for medium resolution and medium-high bandwidth applications.