Designing a Fine-Tuning Tool for Machine Learning with High-Speed and Low-Power Processing

摘要

Machine learning is used in various fields. In order to broaden its further applications, it is necessary to use an architecture that operates faster and with lower-power consumption than conventional architecture. In this paper, as an architecture for that, it is proposed to use the ASIC-FPGA architecture proposed by the authors. In circuits on FPGAs, wave-pipeline techniques can be introduced for further high through put processing. In order to further improve the performance of wave-pipelines on the FPGAs, fine-tuning should be executed. A fine-Tuning tool essential for realizing these is developed.