A 10-bit 16-MS/s Ultra Low Power SAR ADC for IoT Applications

摘要

This paper presents a 10-bit 16MS/s ultra-low-power Successive Approximation Register (SAR) ADC with capacitor array combining the split-capacitor array and monotonic switching procedure. To achieve the ultra-low power requirement, bootstrapped switch, low power capacitor array, dynamic two-stage comparator without any calibration are employed. The chip area is 0.0288mm² based on 55nm CMOS process. At 1MHz input signal and 16MS/s sample rate, the measurement results show that we get 55dB SNDR and 71dB SFDR. The power consumption of ADC core is only about 150uW, resulting in a FOM of 20.3 fJ/conversion-step.