Controlled-Oscillator Optimization for Highly-Digital CMOS Time-Based Sensor-to-Digital Converter Architectures

摘要

This paper presents the theoretical analysis and comparison of two major highly-digital-oriented architectures for sensor interfaces. The first architecture is based on a phase-locked loop, while the second one is count-based. These two time-based topologies have a different working principle, which leads to different VCO requirements in terms of gain linearity (voltage-to-frequency, V-to-f, or voltage-to-period, V-to-T, linearity). To validate the theoretical analysis, a state-variable-based Matlab model has been developed for both architectures confirming that using a VCO with the optimal linear transfer characteristic (V-to-T or V-to-f) is instrumental to achieve the maximum SQNR.