An optimized hardware design of Integer Motion Estimation HEVC for encoding 8K video

摘要

High Efficiency Video Coding (HEVC) is the new video compression standard. A novel optimized architecture of Integer Motion Estimation (IME) for HEVC processing 8K video is presented in this paper. This architecture achieves 8K (7680×4320) video in real time at 43 fps (frames per second) with a frequency of 142MHz and a latency of 402 clock cycles. The proposed design has been synthesized and simulated by Xilinx ISE 14.7 using Virtex-7 28nm technology. Up to now, this is the first IME design reaching 8K video requirements which can be implemented in a FPGA kit in real time.