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Realization and Optimization of Pulse Compression Algorithm on OpenCL-Based FPGA Heterogeneous Computing Platform

机译:基于OpenCL的FPGA异构计算平台脉冲压缩算法的实现与优化

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The development of modern radar signal processing technology put forward higher requirements for processor performance. However, Moore's law encounters bottlenecks, the computational performance of general-purpose processors is constrained and can not meet application requirements. The high-performance and low-power features of FPGA make them recently become of interest in research as a heterogeneous computing platform together with CPU. Pulse compression algorithm is widely used in the field of radar signal processing, which contains a large number of floating-point computing, the processing effect largely depends on the performance of the processor. Based on Open Computing Language (OpenCL), we first evaluated the Fast Fourier Transform (FFT) of various sample sizes on ArrialO FPGA board and FPGA achieve up to 33.5 times the performance improvement compared to DSP C6678 on processing different sample size of FFT. Then we realize a 4 K x 8 K size pulse compression processing using kernel channel. The results show that the core computation implemented on ArrialO FPGA through OpenCL is approximately 10x faster than DSP C6678 for 4 K x 8 K size pulse compression processing.
机译:现代雷达信号处理技术的开发提出了对处理器性能的更高要求。但是,Moore的法律遇到瓶颈,通用处理器的计算性能受到约束,无法满足应用要求。 FPGA的高性能和低功耗特征使它们最近成为与CPU一起作为异构计算平台的研究感兴趣。脉冲压缩算法广泛应用于雷达信号处理领域,其包含大量浮点计算,处理效果在很大程度上取决于处理器的性能。基于开放计算语言(OpenCL),我们首先评估Arrialo FPGA板上的各种样本大小的快速傅里叶变换(FFT),与DSP C6678加工不同样品大小的DSP C6678相比,FPGA可实现高达33.5倍的性能改进。然后,我们使用内核通道实现4 k x 8 k尺寸脉冲压缩处理。结果表明,ArriSo FPGA通过OpenCL实现的核心计算比DSP C6678速度大约为4K x 8 k尺寸脉冲压缩处理。

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